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SLEC CG

SLEC CG

SLEC CG formally verifies PowerPro CG power optimizations.

>Benefits of SLEC CG

  • Comprehensive verification of PowerPro CG results
  • 100% test coverage of all clock gating enable conditions
  • Integrated flow with PowerPro CG to improve verification productivity
  • Eliminates the need for clock gating specific testbench development
  • Replaces time consuming simulation regressions with fast results
  • Isolates bugs quickly with short, concise debug waveforms

Based on Calypto's patented Sequential Analysis Technology, SLEC CG provides efficient, comprehensive verification of PowerPro CG optimized RTL.

SLEC CG formally compares the functionality of the original RTL design with the PowerPro CG optimized RTL design for all possible input sequences. Unlike combinational equivalence checkers, SLEC CG does not require one to one mapping of registers.

SLEC CG confirms that no functional errors exist in any of the clock-gating enable conditions added or modified by PowerPro CG or generates short, concise waveforms that pinpoint design differences. These waveforms are written in standard VCD and FSDB formats that can be analyzed in the user's native debugging environment.

SLEC CG is seamlessly integrated into the PowerPro CG design flow to remove the need for users to specify design files and setup.

SLEC CG is part of Calypto's SLEC family of proven sequential equivalence checking products.