Calypto Newsletter

Message from the Chief Executive Officer

Welcome to the Fall 2009 edition of the Calypto Newsletter where you will find the latest news and information about Calypto and our market leading products.  This issue includes several articles covering the capabilities of our PowerPro and SLEC product families. 

Calypto continues to apply its unique Sequential Analysis Technology to deliver solutions that designers can readily apply to solve critical issues in the SoC design flow.  In June, we announced the availability of PowerPro MG, the industry’s first fully automated, memory power optimization tool for SoC designers.  PowerPro MG applies Sequential Analysis techniques to automatically generate Memory Gating logic that significantly reduces both static and dynamic on-chip memory power.  Similar to PowerPro CG, PowerPro MG fits seamlessly into today’s RTL synthesis flows.  The tool reads in an RTL design as well as the applicable memory models.  Using Calypto’s patented Sequential Analysis Technology, the tool constructs new memory gating logic that works in conjunction with the low-power memory modes to produce the lowest power memory implementation possible.  PowerPro MG then generates new power-optimized RTL that looks identical to the original RTL except for the addition of the new memory gating logic. Aimed at large, complex SoC designs, PowerPro MG has been proven to reduce power consumption in a variety of end applications such as storage, networking, graphics and multimedia.

In August, Calypto announced the application of our Sequential Analysis technology to RTL power analysis, delivering dramatically more accurate results than the decade old RTL power analysis tools in use today. These obsolete tools are based on combinational analysis which limits the accuracy of switching activity propagation compared to the actual sequential circuit activity.  Sequential analysis ensures switching activity propagation estimated by the tool closely correlates with real life circuit activity.  RTL power analysis will be integrated into PowerPro Analyzer, the industry’s leading Graphical User Interface (GUI) for RTL power analysis and optimization. 

Read more >>

What's New in SLEC® 4.0

SLEC® version 4.0 was released on July 17, 2009. The latest version of SLEC contains the following features and enhancements:

• Improvements in the Mentor Catapult, Forte Cynthesizer and Cadence C-to-Silicon integrations.
• Achieved 5x capacity improvements by making significant improvements in various engines including machine acceleration, simulation based validation, constraint and map handling and waveform-dumping which enable it to handle designs with significantly larger throughputs.
• Support for hierarchical-synthesis of C++ functions enabling capacity improvements in C vs. C verification of designs with complex functions.
• Improvements to the bit-level solver, word-level solver and functional-analysis infrastructures within SLEC.
• Support for monitoring the toggle activity of a specified list of signals to flag potentially over-constrained setups.

These new capabilities further reinforce SLEC’s position as the cornerstone of today's advanced high-level synthesis (HLS) design flows. Users should move to SLEC 4.0 as soon as possible.

NEW white paper: Memory Power Reduction in SoC Designs Using PowerPro MG

Memories occupy over 50% of the silicon real estate on most modern SoCs and account for 50-70% of the power dissipation. As such, selecting the optimal memory architecture and ensuring that the memories are controlled to optimize memory accesses is critical to meeting the overall SoC power budget. With power becoming a critical design consideration, memory vendors have been providing more power efficient memory architectures and power modes in their memory IP to enable SoC designers to use power reduction techniques such as sleep modes and dynamic voltage and frequency scaling. Exploiting sleep modes in memories and identifying scenarios where memories may be read or written redundantly requires designers to analyze the memory and the surrounding logic across multiple cycles. In this paper, we survey the key power reduction techniques available in memories designed for 40 and 32 nm process nodes from Virage Logic.  We will show how Calypto’s PowerPro MG tool can significantly reduce the dynamic and leakage power consumption in memories by automatically inserting new memory gating logic to remove redundant reads/writes and control the sleep modes available in these memories.

Read more>>

Calypto in the News

10/15/09 EDA DesignLine - How to Reduce Memory Power in SoC Designs

09/17/09 EDA DesignLine - Verification Alive and Well at SoC Virtual Conference

08/24/09 Calypto Delivers Industry’s First RTL Power Analyzer Based on Sequential Analysis Technology: Achieves RTL-level Power Analysis Results with Gate-level-like Accuracy in a Fraction of the Time

08/11/09 Chip Design -Verification Vertigo Blog- Interview with Tom Sandoval, CEO of Calypto

07/27/09 Calypto Delivers Fully Automated Sequential Optimization Flow for High-performance IP Blocks: PowerPro CG, SLEC RTL Combine with Popular Synthesis Tools to Achieve Power, Performance and Area Goals

07/20/09 Calypto Enables ESL Design and Verification of Complex Designs with 5x Capacity Improvement: Improves HLS Tool Integration to Boost Designer Productivity, Adds Multiple Clock Support

06/22/09 EE Times - Calypto tool lets SoC designers reduce memory power

06/22/09 EDN - Calypto Delivers Industry’s First Automated Tool for Memory Power Optimization

06/09/09 EDA Cafe - Calypto Delivers 'Picture Perfect' ESL Solution to Casio

PowerPro® Tips & Tricks

Bottom Up Flow Methodology

PowerPro CG provides a fully automated approach to reducing power at the RTL level.  Because designs today are generally partitioned into functional hierarchies that can enable more efficient flows, Calypto has ensured that PowerPro CG has all the required features to fit directly into a hierarchical approach to RTL design optimization.  This enables more efficient use of licenses and also allows PowerPro to be used on very large designs.

Consider the following structure of block identified for PowerPro.

Now, let’s assume that PowerPro will be run hierarchically on “Block1” and “Block2” respectively and that the power optimized design will be re-assembled in the context of “Core”.  Consider that module “B” gets optimized differently as a part of PowerPro runs on “Block1” and “Block2”.  This commonly occurs in blocks that are duplicated in a design since the optimizations performed by PowerPro CG are in-context. 

This is where a Bottom-Up Flow Methodology will help the design team to optimize the “Core” design with minimal manual effort. The question here is, “How to resolve file/package/library name conflicts while stitching files generated from PowerPro runs on sub-blocks?”

STRATEGY

Run each sub-block with the following modifications to the standard PowerPro run file.

set TOP Block1
build_design –top $TOP –f  top.f
config_write_rtl                                                                                          \
  -rename_all_modified_modules       yes                                                   \
  -separate_uniquified_module_files  yes                                                   \
  -uniquified_module_naming_scheme                                   ${TOP}_%s  \
  -observability_logic_module_naming_scheme             obs_${TOP}_%s  \
  -observability_logic_instance_naming_scheme        i_obs_${TOP}_%s  \
  -const_stability_logic_module_naming_scheme         cstb_${TOP}_%s  \
  -const_stability_logic_instance_naming_scheme    i_cstb_${TOP}_%s  \
  -sym_stability_logic_module_naming_scheme           sstb_${TOP}_%s  \
  -sym_stability_logic_instance_naming_scheme      i_sstb_${TOP}_%s  \
config_reset_spec  -location                                                           $TOP  \
                                 -reset_hier           ppro_reset_$TOP \
                                 -reset_instance i_ppro_reset_$TOP \

Merging the Optimized Files in Context of “Core”

To merge the files and generate a single filelist

• Creating an absolute filelist

    sort –u */powerpro_rtl*/rtl_mod.f  > rtl_mod.f

• Creating a relative filelist so that the directory can be copied

              cp –i */powerpro_rtl*/*.v merged_dir/

   sort –u */powerpro_rtl*/rtl_mod_rel.f > merged_dir/rtl_mod_rel.f

Please note that you are required to take the rtl_mod.f, rtl_mod_rel.f from the latest directory containing these files.

For instance, if one runs only Observability based optimization, one should pick these files from powerpro_rtl_insert_obs directory. If both Observability and Stability optimizations have been run and PowerPro found both types of optimizations, the directory to work with should be powerpro_rtl_insert_stb_s.

NOTE: Some manual intervention is required in case of VHDL designs as sorting can disrupt the original order of the files.

Message from the Chief Executive Officer (continued)

With all of the user activity surrounding High Level Synthesis (HLS) at DAC this year, it is readily apparent that HLS methodologies are now mainstream and can handle some of the most complex designs in the industry.  Calypto announced the release of SLEC 4.0, featuring algorithmic enhancements to Calypto’s patented word level solvers.  This latest version of SLEC also includes dramatic improvement to SLEC’s proprietary database that results in a reduced memory footprint while SLEC is running.  Together, these advancements enable the tool to handle larger, more complex designs.  Designers can more freely use high level synthesis for the generation of complex functions, knowing that SLEC can provide comprehensive verification.   The interface between SLEC and the leading HLS tools— Mentor Catapult, Cadence C-to-Silicon compiler, and Forte Cynthesizer —has also been improved in SLEC 4.0 to ensure an automated, efficient path to formal verification, requiring little or no user intervention.

I hope you find this latest issue of the Calypto Newsletter to be helpful in understanding Calypto's products and capabilities. The newsletter contains the most recent articles and news from Calypto and our partners. Please contact us at: with any questions or comments.

Best Regards,

Tom Sandoval
Chief Executive Officer
Calypto Design Systems

In This Issue:

• Message from the CEO
• What's New in PowerPro 3.0
• What's New in SLEC 4.0
• SLEC Tips & Tricks
• PowerPro Tips & Tricks
• NEW White paper: Memory Power Reduction in SoC Designs Using PowerPro MG
• Calypto In the News
• Product Information

Calypto is now on Twitter!

What's New in PowerPro® 3.0

PowerPro 3.0 was released on August 31, 2009. This release includes several new enhancements and features including:

• PowerPro MG:
  • Automated memory power optimization to automatically reduce dynamic and leakage power in memories.
• PowerPro CG:
  • Several new and more powerful observability and stability based optimizations have been provided to achieve more power savings.
  • Support for ECO of observability as well as stability based power optimization has been released.
  • Enhanced support for reading in Verilog or VHDL designs and writing out optimized RTL with power saving changes.

For a complete list of features and enhancements, please check the release notes or user’s manual included in the software release package.

SLEC® Tips & Tricks

Debugging Problem Setup Issues

In some cases SLEC will find a falsification where the source of the difference is not due to any design differences but is caused by an incorrect problem setup. The problem setup includes everything which is used to specify how the designs are to be verified:

• Design parameters values: throughput, latency and reset length.
• Constraints: used to define the operation of reset or used to constrain only certain modes of operation.
• Transactors: design elements instantiated to define complex constraints such as one-hot to some encoded state.
• Blackboxes: internal blocks which may be removed from the analysis.

If the problem setup has not been specified correctly, the two designs may be analyzed in different modes of operations with no chance of them being equivalent or with values of throughput or latency, for example, which are different from the actual design behavior, again ensuring a falsification.

This article explains how to quickly verify the problem setup is correct.

The first indication that the issue may be related to problem setup is typically that the design falsifies during simulation based validation (SBV). Before the formal solvers are used, SLEC performs analysis using the SBV engine (unless it is explicitly disabled). If a falsification is found during SBV it typically means it was an easy problem to find or that there is an issue with the problem setup, since issues with problem setup tend to manifest themselves quickly: the two designs begin to behave differently after only a few cycles.

When the formal solvers begin their analysis, SLEC outputs the following message: “Started sequential analysis”. Even if a design difference is found by the formal solvers it could still be a problem setup issue and the following steps are good first steps in any debug process.

Review the log files.

• mapping.log: ensure all the inputs are correctly mapped. If the input port names are different in each design they will need to be explicitly mapped to ensure both designs are driven by the same data. Some inputs may require a map with latency, for cases where one design expects the same input N cycles after the other (with respect to the end of reset).
  
  
• bbox.log: confirm both designs have the same blocks specified as blackboxes or that one of designs correctly has additional functionality removed by blackboxing.
  
  

• ccheck_spec.log, ccheck_impl.log and reset.log: review these files to confirm there are no sources of unknown (‘hX) values such as un-driven input pins or flops which start as unknown and propagate unknown values (‘hX) into the design. Review the SLEC User Guide for special handling of unknown (‘hX ) values in the design.

A useful technique before proceeding to check the design setup parameters is to enable the SLEC auxiliary signals. The auxiliary signals are written to the VCD files and show when SLEC applies the 1st , 2nd, 3rd, etc. input values to each input port and checks the corresponding 1st, 2nd, 3rd, etc. output values of each output port. In cases where the designs have different throughputs or latencies, the auxiliary signals significantly help with the ability to align the waveforms of the two designs for detailed analysis.

• If the designs are cycle accurate with a throughput of one, such as in an RTL-to-RTL comparison, the following check can be ignored. Check any internal state elements which are affected only by the clock or reset (no other inputs, even via internal signals, affect their operation or behavior). Good candidates are state/FSM vectors, counters, output or input handshakes. Adjust the throughput to ensure these elements repeat every transaction (as defined by the throughput) and return to the same state at the start of each transaction.
  
  
• Verify the reset length for both designs is correct. The auxiliary signal trans_start shows when the first input data is applied on the input ports. This is done at the end of the specified (or default) reset phase. If one design requires for example 4 clocks before it is ready to accept an input, specify the reset length as 4, or the inputs will be applied too early, ensuring a difference in behavior.
  
  
• Confirm that the latency specified for each design, or specified individually for each port, is correct. The auxiliary signals can be used to compare one design with another. For example, the 1st output for each port will be compared when the associated (by name) auxiliary signal has the value 1. The 2nd output compared when the auxiliary signal has value 2 etc.
  
  
• If transactors are used at the input and output, confirm the data is being correctly transformed by the transactor: check the waveforms at both the inputs and outputs of the transactor.

If the above items appear correct, it is likely the falsification is due to a genuine design difference and a more focused detailed debug effort may be required to determine the exact nature of the difference.

Product Information

PowerPro® MG
PowerPro MG is an automated memory power optimization solution that takes advantage of the low-power control options available in today’s on-chip memories to reduce both dynamic and leakage memory power with little or no impact to timing or area. PowerPro MG reduces dynamic power by automatically generating logic to control the memory enable signal to eliminate unnecessary memory accesses. 
Read more >>

PowerPro® CG
Based on Calypto’s patented Sequential Analysis Technology, PowerPro CG reduces power by up to 60% in RTL designs. PowerPro CG evaluates circuit behavior across multiple clock cycles to identify sequential clock gating enable conditions. New enable logic is inserted into the original RTL code while maintaining all user defined pragmas and comments.
Read more >>

PowerPro® Analyzer
PowerPro Analyzer is the industry’s most accurate register-transfer level (RTL) power analysis tool. PowerPro Analyzer performs sequential analysis of the entire design, delivering power measurement results that are significantly more accurate than the decade-old RTL power analysis tools in use today.
Read more >>

SLEC® System
Enabling ESL™
SLEC System finds design errors that other tools miss by formally comparing the functionality of an Electronic System Level (ESL) model written in C/C++/SystemC with its corresponding RTL design or system-level model for all possible input sequences. Unlike combinational equivalence checkers, SLEC System does not require one to one mapping of registers. The quality of verification SLEC System performs in minutes is equal to months of running simulation.
Read more >>

SLEC® System-HLS
SLEC System-HLS finds design errors that other tools miss by formally comparing the functionality of a system level model written for HLS with its corresponding synthesized RTL design across all possible input sequences. SLEC System-HLS increases design productivity through automated setup and elimination of block-level RTL simulation.
Read more >>

SLEC® RTL
SLEC RTL finds design errors that other tools miss by formally comparing the functionality of the original RTL design and the corresponding optimized RTL design for all possible input sequences. Unlike combinational equivalence checkers, SLEC RTL does not require one to one mapping of registers. SLEC RTL is ideal for verifying RTL changes for retiming and clock gating, allowing designers to confidently make complex changes to their RTL to meet today’s aggressive power and performance design goals.
Read more >>

SLEC® Pro
SLEC Pro provides efficient, comprehensive verification of PowerPro optimized RTL. SLEC Pro formally compares the functionality of the original RTL design with the PowerPro optimized RTL design for all possible input sequences. Unlike combinational equivalence checkers, SLEC Pro does not require one to one mapping of registers.
Read more >>

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