Calypto Newsletter
Message from the Chief Executive Officer
Welcome to the Winter 2008 edition of the Calypto Newsletter. We have been working hard to expand the capabilities of our PowerPro CG and SLEC products. Please read on to learn more about what’s new with Calypto and our products.
The demand for PowerPro CG continues to grow. Over 200 customer designs have been run through PowerPro CG with power reduction of up to 60%. Our latest 2.1 release further expands the power optimization capability of PowerPro CG with new transformations that deliver additional power reduction in designs that are already heavily clock gated. This is especially useful in existing functional blocks that have been manually clock gated and will be re-used in new, more power sensitive applications. We have also found that HLS generated RTL designs tend to be heavily clock gated. PowerPro CG’s new transformations will also be very effective in reducing power for those machine generated designs.
The latest PowerPro CG release also supports VHDL design flows. We have been working closely with VHDL customers for several months to ensure our support is robust and able to handle sophisticated VHDL coding styles. With this support in place, PowerPro CG’s applicability now extends into design teams in European consumer and wireless electronics companies where VHDL is the dominant language.
What's New in SLEC 3.2
SLEC™ version 3.2 was released on November 1st 2008. The latest version of SLEC supports fixed-point datatypes and system-level memory interfaces commonly used in wireless, video and image processing system-on-chip (SoC) designs. These new capabilities further reinforce SLEC’s position as the cornerstone of today's advanced high-level synthesis (HLS) design flows.
The latest release of SLEC supports ac_fixed and cynw_fixed dataypes that are commonly used in wireless designs to model digital signal processing algorithms such as Fast Fourier Transforms and Reed Solomon decoders. SLEC comprehensively verifies the register transfer level (RTL) implementation generated by HLS without running time consuming simulations. Similarly, SLEC supports ac_windows and external memory interfaces which simplify system-level modeling of computations on large data frames typical in H.264 codec and edge detection designs.
Extensive feedback from many users has been incorporated into the SLEC 3.2 release. This latest release also provides enhanced waveform analysis options and support for arbitrary-point black boxes to allow direct detailed analysis of signals and blocks deep within complex SoC designs to further reduce the debug cycle and improve productivity.
Users should move to SLEC 3.2 as soon as possible.
Calypto in the News
10.27.08 - EDA Cafe - Calypto's PowerPro CG Cuts Power Consumption in Pixim's Latest Video Image Processor
10.22.08 - Design & Reuse - Calypto, Forte Collaboration Results in Advanced SystemC Design Flow
10.20.08 - SOCcentral - Calypto Strenghtens PowerPro CG with New Power Optimizations, VHDL Support
09.09.08 - EDA DesignLine - Reducing Power Consumption in a Fiber Switch
08.04.08 - Calypto's PowerPro CG Selected by AMD to Reduce Power in Processor Designs
Product Information
PowerPro CG
Based on Calypto’s patented Sequential Analysis Technology, PowerPro CG reduces power by up to 60% in RTL designs. PowerPro CG evaluates circuit behavior across multiple clock cycles to identify sequential clock gating enable conditions. New enable logic is inserted into the original RTL code while maintaining all user defined pragmas and comments.
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SLEC System
Enabling ESL™
SLEC System finds design errors that other tools miss by formally comparing the functionality of an Electronic System Level (ESL) model written in C/C++/SystemC with its corresponding RTL design or system-level model for all possible input sequences. Unlike combinational equivalence checkers, SLEC System does not require one to one mapping of registers. The quality of verification SLEC System performs in minutes is equal to months of running simulation.
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SLEC System-HLS
SLEC System-HLS finds design errors that other tools miss by formally comparing the functionality of a system level model written for HLS with its corresponding synthesized RTL design across all possible input sequences. SLEC System-HLS increases design productivity through automated setup and elimination of block-level RTL simulation.
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SLEC RTL
SLEC RTL finds design errors that other tools miss by formally comparing the functionality of the original RTL design and the corresponding optimized RTL design for all possible input sequences. Unlike combinational equivalence checkers, SLEC RTL does not require one to one mapping of registers. SLEC RTL is ideal for verifying RTL changes for retiming and clock gating, allowing designers to confidently make complex changes to their RTL to meet today’s aggressive power and performance design goals.
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SLEC CG
SLEC CG provides efficient, comprehensive verification of PowerPro CG optimized RTL. SLEC CG formally compares the functionality of the original RTL design with the PowerPro CG optimized RTL design for all possible input sequences. Unlike combinational equivalence checkers, SLEC CG does not require one to one mapping of registers.
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PowerPro Tips & Tricks
This PowerPro tip describes how switching activity is used to rank clock-gating optimizations and how to make sure your SAIF file is properly annotated onto your design.
PowerPro CG uses sequential analysis technology to identify clock gating conditions that do not impact design functionality. However, not all clock-gating enable conditions are equally effective in reducing power.
After PowerPro CG completes the sequential analysis of the design to identify all possible clock-gating enable conditions, it ranks the power saving potential of each clock gating condition by analyzing design switching activity and computing the improvement in clock-gating efficiency. Clock-gating efficiency is the percentage of time (percentage of clock cycles) a register's clock is disabled (gated) for a given switching activity file (SAIF). The switching activity file, or SAIF file, is provided by the user and should be based on a simulation that represents the use of the design in a real application. A SAIF file can be either generated from the simulator directly or created from a VCD file via a VCD2SAIF utility.
The SAIF file information is used by PowerPro CG to compute the improvement in clock gating efficiency for each new clock gating enable condition. Using area, timing, and improvement in clock-gating efficiency, PowerPro CG then makes a cost based trade-off to determine which enable conditions to commit to the optimized design.
If switching activity data is not available, PowerPro CG has a vector-less mode which will propagate statistical switching activity to calculate clock-gating efficiency information. The vector-less mode can be configured to be more representative of actual application behavior by specifying ports that are constant using the “set_sa” command. (More information on running in vector-less mode can be found in the PowerPro CG user manual)
When using a SAIF file to specify switching activity, it is important to ensure the SAIF information has been properly annotated in PowerPro CG. After PowerPro CG reads the SAIF file, you should always look at the percentage of asserted sequential inputs and outputs. This information is found in the powerpro.log file.
[PA-RSS]
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Asserted Primary inputs in design : 173 (100%)
Total Primary inputs in the design : 173 (100%)
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Asserted sequential outputs : 750 (100%)
Total sequential outputs : 750 (100%)
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Total nets in the design : 4882 (100%)
Net asserted : 1767 (36.19%)
Clock nets : 1 (0.02%)
Constant nets : 0 (0%)
Net does not have saif asserted : 3115 (63.80%)
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"Asserted" refers to the percentage of inputs, sequential outputs (register outputs), and nets that are directly annotated from the SAIF file (as opposed to propagated). You should expect that 100% of “inputs” and close to 100% of “sequential outputs” are asserted. If either of these numbers fall below 95%, there may be a problem with SAIF annotation that requires debugging. A low “net asserted” percentage is not a problem since our switching propagation engine will take care of ensuring nets are annotated with the correct information as long as there is 100% of “inputs” and greater than 95% of “sequential “outputs” asserted.
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Message from the Chief Executive Officer (continued)
Through recent evaluations, it has become more evident that PowerPro offers a unique capability not available from any other EDA vendor. Although others have claimed automated RTL power optimization, we have several examples of where PowerPro CG’s unique power saving capabilities has blown away any potential competition. These capabilities include:
- Identification and insertion of sequential clock gating enable logic
- Generation of RTL that is identical to the user’s RTL with the addition of sequential clock-gating enable logic
- Comprehensive formal verification of optimizations using sequential logic equivalence checking
Customer usage of SLEC also continues to expand. SLEC is the only commercially available sequential equivalence checking product. Support for system-level languages such as C/C++ and SystemC as well as VHDL and Verilog enable a broad set of use models such as verifying equivalence between two system-level models, verifying the RTL generated from high-level synthesis and ensuring RTL level retiming and clock-gating optimizations do not introduce bugs.
We are continuously working with our partners and mutual customers to ensure SLEC System-HLS is compatible with the latest features in Forte’s Cynthesizer, Mentor’s CatapultC, and Cadence’s C-to-Silicon HLS products. The latest version of SLEC (V3.2) includes support for fixed-point datatypes and system-level memory interfaces commonly used in wireless, video and image processing system-on-chip (SoC) designs.
As companies look to improve the efficiency of their design teams, the use of HLS provides obvious benefits. When coupled with SLEC verification, HLS design methodologies can provide up to 10X efficiency improvement over traditional RTL design and verification methods. This has been proven by SoC design teams at several leading electronics companies.
I hope you find this latest issue of the Calypto Newsletter to be helpful in understanding Calypto's products and capabilities.
The newsletter contains the most recent articles and news from Calypto and our partners.
Please contact us at: with any questions or comments.
Best Regards,
Tom Sandoval
Chief Executive Officer
Calypto Design Systems
December 2008 Issue
PowerPro 2.1 Now Available!PowerPro CG 2.1 was released on October 3rd, 2008. This release includes several new enhancements and features including:
The new sequential optimizations are most beneficial for heavily clock-gated designs and designs where the datapath and its corresponding control logic have unrelated enable conditions. RTL generated from HLS tools are excellent candidate designs for these new optimizations. Support for VHDL design flows in PowerPro CG extends the benefit of automated RTL power savings to more designers. PowerPro handles both VHDL87 and VHDL 93 styles and generates an optimized VHDL design which is identical to the original VHDL design except for the additional clock-gating enable logic. Several enhancements have been made to the PowerPro Analyzer. These include show fanin, fanout, driver and load as buttons along the top menu bar. These capabilities are also selectable by double clicking ports in the schematic window. Sequential clock-gating enable conditions are now grouped by domain and can be individually selected and displayed in the new sequential domain view. For a complete list of features and enhancements, check out the release notes or user’s manual included in the software release package. SLEC Tips & TricksReset States in SLECSequential logic equivalence checking proves that for all combinations of inputs, both designs produce the same output over all time. Implicit in this definition is the requirement that both designs start in corresponding equivalent states. That is, both designs are in a state from which they are expected to operate with the same behavior. In SLEC, we call this the reset state and in most cases this matches the hardware reset state in your design. In order to achieve the reset state, SLEC divides the verification into two phases: the first is the reset phase and the second is normal operation. This allows the user to separate the constraints needed to reset the design from those needed for normal operation. Constraints in the form of waveforms are used to achieve the reset state. This allows SLEC to support any arbitrary reset sequence such as loading a RAM with specific values or clocking a state machine a certain number of times to reach the reset state. To specify a reset sequence you must:
PowerPro-filer Available Now!Have you ever wondered how well your RTL design is clock gated? PowerPro-filer is a standalone utility for Verilog design blocks that calculates clock-gating efficiency and the percentages of registers clock gated. Clock-gating efficiency is the percentage of time (percentage of clock cycles) a register's clock is disabled (gated) for a given switching activity file (SAIF). Since clock-gating efficiency takes into account switching activity, it is a much better indicator of clock gating effectiveness and dynamic power savings than the percentage of registers with clock gates. PowerPro-filer
PowerPro-filer can be downloaded from the Calypto website, FREE of charge. www.calypto.com/powerprofiler.php SLEC Tips & Tricks (continued)Here is a simple example. For most designs, the reset state is achieved by asserting the reset port for one clock. Normal operation occurs when reset port is then de-asserted. The following SLEC tcl commands achieve this reset sequence: set_reset_length –spec –clock clk –length 1create_waveform –bitwidth 1 { 1 } –name RESET_ON_1_CLOCKcreate_waveform –bitwidth 1 { 0+} –name RESET_OFF_FOREVERcreate_constraint –reset -waveform RESET_ON_1_CLOCK spec.resetcreate_constraint –reset -waveform RESET_ON_1_CLOCK impl.resetAdditional constraints are specified to ensure the design is not reset during normal operation. This is done using the same create_constraint command, but without the specifying the –reset option. create_constraint –waveform RESET_OFF_FOREVER spec.resetcreate_constraint –waveform RESET_OFF_FOREVER impl.resetAt the end of the reset phase, both designs will be in the reset state. The plus symbol (+) indicates the value 0 is to be applied forever. With the reset port de-asserted, SLEC can now use formal sequential equivalence engines to verify that all combinations of all inputs produce the same output for all time. Not all designs are reset by a simple, single cycle pulse. The following example shows how other, more complex reset sequences can be modeled using waveforms and the create_constraint command. set_reset_length –spec –clock clk –length 3create_waveform –bitwidth 1 { 1 0 0 } –name RESET_rsetcreate_waveform –bitwidth 16 { S 16’h77 16’hFF } –name RESET_rvalcreate_constraint –reset -waveform RESET_rset spec.resetcreate constraint –reset –waveform RESET_rval spec.rvalIn this example, the reset takes three clock cycles during which the reset port goes high for the first clock cycle, then stays low for 2 clock cycles while specific data values (77 Hex and FF Hex) are placed on the input port rval. The value “S” in the RESET_rval waveform specifies a symbolic value, which means SLEC will apply every legal value in the range: 0 to 32768 (216-1) Getting both designs into the same reset state can be tricky. If you see SLEC generate a falsification within the first cycle of verification, chances are that there is problem with the reset sequence in one or both designs. PowerPro Tips & Tricks (continued)The most common reason PowerPro CG reports that asserted “inputs” or “sequential outputs” percentage are less then 95% is that the pathnames in the PowerPro CG database and SAIF file do not match so the data could not be annotated. This typically happens if a wrapper has been added to the design to express dont_care conditions. Since the wrapper is not present in the design, it is not part of the pathnames in the SAIF file. To resolve this problem, specify the additional instance in the design by using the –target_instance in the “read_saif” command. |
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