Calypto Quarterly Newsletter

Calypto Newsletter

Message from the Chief Executive Officer

Calypto's CEO, Tom SandovalWelcome to the latest edition of the Calypto Newsletter where you’ll find the latest news and information about Calypto and our market leading products.  Let’s get right into it.

Calypto closed out its 2008 financial year with record growth.  License counts for both SLEC and PowerPro CG more than doubled, and bookings increased by over 250% compared to the 2007 financial year.  The market clearly understands the unique value our products deliver and usage for both PowerPro CG and SLEC is growing at a very exciting pace.

DAC 2008 turned out to be the best DAC yet for Calypto.  Just prior to the show, we announced the availability of an RTL power optimization flow that integrates PowerPro CG with Encounter® RTL Compiler from Cadence Design Systems, Inc. There was overwhelming interest from SoC designers in this solution which produces the lowest power gate level design while still meeting all timing and area constraints.  Visitors to our booth confirmed that Calypto’s ability to deliver  RTL power optimization and sequential logic equivalence checking is unique in the industry.

Read more >>

Calypto in the News

07.14.08 - SOCcentral - Calypto's SLEC product supports New Cadence C-to-Silicon Compiler

07.08.08 - Calypto Selects Saline as its Distributor in Korea

05.23.08 - Calypto Delivers Optimized Power Flow with Cadence

05.14.08 - Calypto Names Maojet as its Distributor in Taiwan

05.13.08 - Calypto Selects AST Ltd. as its Distributor in Isreal

05.06.08 - DesignLine - More good news: Calypto reports record bookings

Technical Case Studies

We have posted several new case studies on our website. You can download our case studies and customer success stories to see how market leaders are taking advantage of our unique solutions at:

www.calypto.com/customersuccess.php

Product Information

PowerPro CG
Based on Calypto’s patented Sequential Analysis Technology, PowerPro CG reduces power by up to 60%. PowerPro CG evaluates circuit behavior across multiple clock cycles to identify sequential clock gating enable conditions. New enable logic is inserted into the original RTL code while maintaining all user defined pragmas and comments.
Read more >>

SLEC System
Enabling ESL™
SLEC System finds design errors that other tools miss by formally comparing the functionality of an Electronic System Level (ESL) model written in C/C++/SystemC with its corresponding RTL design or system-level model for all possible input sequences. Unlike combinational equivalence checkers, SLEC System does not require one to one mapping of registers. The quality of verification SLEC System performs in minutes is equal to months of running simulation.
Read more >>

SLEC System-HLS
SLEC System-HLS finds design errors that other tools miss by formally comparing the functionality of a system level model written for HLS with its corresponding synthesized RTL design across all possible input sequences. Unlike combinational equivalence checkers, SLEC System-HLS does not require one to one mapping of registers. SLEC System-HLS increases design productivity through automated setup and elimination of block-level RTL simulation.
Read more >>

SLEC RTL
SLEC RTL finds design errors that other tools miss by formally comparing the functionality of the original RTL design and the corresponding optimized RTL design for all possible input sequences. Unlike combinational equivalence checkers, SLEC RTL does not require one to one mapping of registers. SLEC RTL is ideal for verifying RTL changes for retiming and clock gating, allowing designers to confidently make complex changes to their RTL to meet today’s aggressive power and performance design goals.
Read more >>

SLEC CG
SLEC CG provides efficient, comprehensive verification of PowerPro CG optimized RTL. SLEC CG formally compares the functionality of the original RTL design with the PowerPro CG optimized RTL design for all possible input sequences. Unlike combinational equivalence checkers, SLEC CG does not require one to one mapping of registers.
Read more >>

PowerPro Tips & Tricks

In this edition of the newsletter we discuss ways to maximize the capabilities of PowerPro CG scripts and PowerPro Analyzer. PowerPro CG is controlled through TCL scripts. In the powerpro/examples directory, there are several TCL scripts that can serve as a starting point when running PowerPro CG for the first time. As you develop your scripts, consider coding for reuse so they can be used on future design blocks. Here are some scripting hints to incorporate into your design flow.

1) You should avoid using hard paths to files and directories. Instead, base file names on the current working directory. To locate the directory where PowerPro is being run use the command: 

[pwd]

2) You can simplify your scripts by moving useful or repeated tasks into procedures. To make these procedures available to all PowerPro CG runs, add them to the .powerprorc file in your home directory. This file, if it exists, is sourced every time PowerPro CG starts. Here is an example of a simple procedure that opens the graphical Analyzer. 

proc gui {
       show_analyzer
}

Then type gui in the PowerPro CG shell to display the PowerPro Analyzer.

Ppro> gui

3) A useful task when setting up PowerPro CG is to check the completeness of SAIF annotation. The following procedure, check_primary_input_sa_assertion, displays the SAIF annotation on primary inputs after the read_saif command has been called. 

proc check_primary_input_sa_assertion {} {
    foreach input [find -port -input] {
        set data [ltail [get_info -datatype [find -input -port $input -id]]]
        set bit_type [lindex [split $data] 1]
        if { [string equal $bit_type bit] == 1 } {
              set width 1
         } else {
             set upper_bound [lindex [split $bit_type :] 0]
             set lower_bound [lindex [split $bit_type :] 1]
             set width [expr $upper_bound - $lower_bound + 1]
         }
         if { ![string eq "SA prob value" [get_sa -prob -assertion_type -port $input]] ||
              ![string eq "SA td value" [get_sa -td -assertion_type -port $input]]} {
                 puts "SA data does not exist on PI:$input WIDTH:$width "
        }
    }
 }

Now type check_primary_input_sa_assertion in the PowerPro CG shell to display the SAIF annotations for all primary inputs. By observing the level of switching activity, you can identify deficiencies or problems in the SAIF file annotation.

The PowerPro Analyzer has many useful shortcuts if you know where to click. Here are a few that simplify common tasks.

1) When displaying clock gating moves in the PowerPro Analyzer, it is useful to sort the data in ascending/descending order, i.e. sorting CG domains by clock gating efficiency. To sort a list, simply click on any tab in the Clock Gating Report window and the list will be sorted by that category and redisplayed. Clicking on the same tab a second time reverses the order of the list.

2) To display a clock gating move in the source or schematic window, click on the flop in the Clock Gating Report window. The RTL source code window will highlight the corresponding code. If you want to see the flop in the Schematic window, click on the CG domain before clicking on the flop.

3) There may be times when you want to selectively choose clock gating moves for future runs of PowerPro CG. To select a clock gating move, click the check-box in front of the domain id. Once you have chosen all the moves you want to save, then select the Report -> Set Optimize Script menu which will save the moves into a TCL file. The saved file is sourced just before sequential analysis in subsequent PowerPro CG runs to use the selected moves.

Contributed by Amit Goldie, Sr. Member of Technical Staff

Message from the Chief Executive Officer (continued)

Calypto’s SLEC System product was at the center of the ESL discussion at DAC with ST Microelectronics’ announcement of a certified ESL design flow that includes Calypto’s SLEC System and SLEC System-HLS products.  Adoption of HLS continues to accelerate as evidenced by the increased interest in HLS (High Level Synthesis) combined with SLEC System-HLS, the industry’s defacto formal verification solution.

Last week, we announced a new version of SLEC System-HLS that is integrated with Cadence® Design Systems’ new C-to-Silicon Compiler high-level synthesis product.  The announcement included a quote from Hisaharu Miwa, general manager of Design Technology Division, Renesas Technology Corp. who stated, “The industry requires formal equivalence checking in high-level synthesis flows.  We found that the Calypto SLEC System-HLS and Cadence C-to-Silicon Compiler integration provides us an excellent system-level formal verification flow, saving our design team significant time and maximizing productivity.”  Testimonials like this one are common from our SLEC System-HLS customers who see the dramatic improvement in productivity from a combined High Level Synthesis and Formal Verification flow.

I hope you find this latest issue of the Calypto Newsletter to be helpful in understanding Calypto's products and capabilities. The newsletter contains the most recent articles and news from Calypto and our partners. Please contact us at: with any questions or comments.

Enjoy the summer!

Best Regards,
Tom Sandoval
Chief Executive Officer
Calypto Design Systems

July 2008 Issue

Introducing PowerPro-filer

Have you ever wondered how well your RTL design is clock gated?

PowerPro-filer is a standalone utility for Verilog design blocks that calculates Clock-Gating efficiency and the percentages of registers clock gated. Clock-Gating efficiency measures the percentage of time a register is gated (turned off) for a given set of activity vectors. Since Clock-Gating Efficiency takes into account switching activity, it is a much better indicator of clock gating effectiveness and dynamic power savings.

PowerPro-filer can be downloaded from the Calypto website, FREE of charge.

PowerPro-filer

  • Gives designers insight into RTL power savings opportunities
  • Generates clock-gating stats for RTL design blocks
  • Uses switching activity to report clock-gating activity
  • Guides power optimization efforts

Download your FREE copy of PowerPro-filer today at: www.calypto.com/powerprofiler.php

SLEC Tips & Tricks

Using Auxiliary Signals for Debug

SLEC verifies that two designs are equivalent even if they have different reset sequences, throughputs and/or latencies. However, these parameters must be correctly specified for SLEC to know when and how to compare the designs. In this edition of the Tips & Tricks, we discuss how the SLEC auxiliary signals can be used to confirm that the designs have been correctly setup in terms of reset length, throughput and latency.

The SLEC auxiliary signals are enabled by specifying the following command in your Tcl file:

config_trace_files -auxsignals

When enabled, the auxiliary signals are written into the waveform trace files (VCD or FSDB format) and show where reset ends, inputs are applied and outputs sampled.

The auxiliary signal "trans_start" can be used to determine the design throughput since it increments every N cycles, where N is the design throughput of that design.

The "MAP_NAME_check" signals show where the outputs or flops are compared: "MAP_NAME" is the name of the map (typically the same as the port name) and the signal increments after L cycles and then every N cycles (L is the latency of that map and N the throughput of that design).

Even if both designs have very different throughput and latencies, these auxiliary signals allow you to align the designs and confirm that the inputs are applied and outputs are compared at the correct time.

Read more >>

Power Optimization in an RTL Design Flow with Cadences' Encounter RTLCompiler

Power-saving optimizations effect design timing and area, however most of the time the impact is within design constraints. It is important to understand the implementation consequences of adding power saving logic to minimize power and still meet timing and area goals.

By working at the RT Level designers have greater opportunities to reduce power. However, at the RT Level the relationship between power, timing and area is not always intuitive. Consequently, designers making RTL power optimizations tend to be conservative, unsure if they have left significant power savings on the table.

The integration of PowerPro CG and Encounter RTL Compiler from Cadence Design Systems solves this problem by providing a single-pass flow that creates the lowest power design while still meeting timing and area constraints.

Read more >>

SLEC Tips & Tricks (continued)

Reset Length

The signal "trans_start" will be 1 on the first active edge of the clock after reset. The inputs applied during this cycle (sampled on this clock) will be the first valid inputs to the design. Both designs get the same data when "trans_start" is 1. The important point to confirm is that data is applied at the correct time in both designs.

If one of the designs is still in the process of being reset, it will not be able to accept these first set of input values. It will use some later values as it's first inputs, which will result in a falsification. Alternatively, if one of the designs has already finished its reset sequence, previous inputs may be used as the first set of valid inputs, again resulting in a falsification.

The "trans_start" signal changes to 1 where SLEC has been told the reset ends. Confirm that the reset sequence for both designs has indeed ended and this is the first valid clock. If necessary, adjust the reset length using the set_reset_length command or by modifying the reset waveform.

Latency

For each mapped point (flop or output port), when the "MAP_NAME_check" signal transitions, the same values should be present on the respective port/flop for that design.

This auxiliary signal shows where SLEC compares equivalence between the signals. Confirm by looking at the waveforms that this is indeed the correct latencies for both designs. For example, if the output was expected to be 55H but falsified and by examining the waveforms you see 55H on the same signal 3 cycles later, perhaps the latency on that design needs adjusted (increased by 3 in this example).

By looking over multiple cycles, you are more likely to be able to see patterns like this. To control the simulation waveforms refer to the command "create_trace_files -simdump" and globals "sim_max_transactions" and "sim_finds_only_earliest_mismatches".


Throughput

The "trans_start" signal shows the throughput setting in both designs. When trans_start transitions (0 to 1, 1 to 2, etc.), both designs will get the same input data applied (input maps with latency L will mean the signal value changes L cycles after trans_start transitions).

Again, the key point is to confirm that this is the correct time for the new inputs to be applied. Examine the waveforms and ensure both designs are indeed expecting new inputs at the point where "trans_start" changes.

Contributed by Duncan MacKay
Sr. Member of Consulting Staff

Power Optimization in an RTL Design Flow (continued)

Integrating PowerPro CG’s sequential analysis capability and the multi-objective synthesis of Encounter RTL Compiler, the flow optimizes sequential RTL clock gating by incorporating accurate timing information in the power/performance trade-off analysis.

PowerPro CG adds new enable logic to the original RTL code while maintaining the user's comments, style and synthesis pragmas. This ensures the output from PowerPro CG flows directly into RTL Compiler synthesis where enables are translated into efficient combinational logic and clock gating cells. In addition, PowerPro CG creates a Common Power Format (CPF) file that contains enable logic information. This file is used by Encounter RTL Compiler during synthesis. Power and performance tradeoffs are made during synthesis and the enable logic is optimized. If any enable conditions do not meet timing, RTL Compiler prunes or removes those enables from the generated netlist. The end result is a highly power optimized gate-level implementation that meets the users design constraints.

The integration between PowerPro CG and Encounter RTL Compiler automatically creates the lowest power implementation, removing the guess work of manual RTL power optimization methods.

Contributed by Mitch Dale, Director of Product Marketing

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