Calypto Quarterly Newsletter

Calypto Newsletter

Message from the Chief Executive Officer

Calypto's CEO, Tom Sandoval

2008 is moving along at an amazing pace and Calypto has been moving right along with it. Both PowerPro and SLEC are exceeding our expectations in terms of customer adoption. With the increasing usage of High Level Synthesis and the growing need to reduce power in SoC's, Calypto is well positioned to continue its extraordinary market growth.

In March, we released PowerPro CG 2.0, featuring new sequential clock gating optimizations that extend its power saving capability to a wider range of design applications. The 2.0 release includes PowerPro Analyzer, a graphical visualization tool that enables designers to rapidly analyze power optimizations.

PowerPro CG has demonstrated power savings in many different applications including graphics, networking, multimedia, and wireless. The accelerating adoption rates of PowerPro CG/SLEC CG have validated the ease with which our customers have been able to integrate these products into their existing design flows.

As a reflection of Calypto's growth and the unique capabilities we provide to the EDA market, we have changed Calypto's tag line to "Empowering the Next Level of Design". By employing our unique Sequential Analysis Technology to address today's most difficult SoC design challenges-namely RTL functional verification and power optimization-Calypto is empowering our customers to take their design ideas above and beyond what was previously possible.

Read more >>

Calypto Unveils a New Website

Check out www.calypto.com to see Calypto's redesigned website. Our new website features new content and the latest Calypto news.

Let us know what you think at: calypto_info@calypto.com

PowerPro CG 2.0 NOW Available

PowerPro CG 2.0 was released on April 24, 2008. This release includes PowerPro Analyze, a graphical visualization tool with hyperlinked source code, schematics and clock-gating views that enable users to rapidly navigate the power optimizations generated by PowerPro CG.

PowerPro CG 2.0 also contains several other new features as well as many enhancements. They include the integration of PowerPro CG into low-power RTL synthesis design flows. PowerPro CG's write_rtl capability inserts sequential clock gating enable logic into the original RTL code, preserving comments and pragma so that RTL synthesis scripts continue to work without requiring any modifications. Additionally, the output of write_rtl is configurable. For example, the syntax of signal names and ports added by PowerPro CG can be configured to look like the signal names and ports in the original code.

PowerPro CG was originally designed with an extensible architecture to accommodate additional sequential clock gating transformations. PowerPro CG 2.0 features new transformations that extend its power savings capability to a wider range of design applications such as storage and processor designs.

Contributed by Mitch Dale
Director of Product Marketing

Product Information

PowerPro CG
Based on Calypto’s patented Sequential Analysis Technology, PowerPro CG reduces power by up to 60%. PowerPro CG evaluates circuit behavior across multiple clock cycles to identify sequential clock gating enable conditions. New enable logic is inserted into the original RTL code while maintaining all user defined pragmas and comments.

SLEC System
Enabling ESL™
SLEC System finds design errors that other tools miss by formally comparing the functionality of an Electronic System Level (ESL) model written in C/C++/SystemC with its corresponding RTL design or system-level model for all possible input sequences. Unlike combinational equivalence checkers, SLEC System does not require one to one mapping of registers. The quality of verification SLEC System performs in minutes is equal to months of running simulation.

SLEC System-HLS
SLEC System-HLS finds design errors that other tools miss by formally comparing the functionality of a system level model written for HLS with its corresponding synthesized RTL design across all possible input sequences. Unlike combinational equivalence checkers, SLEC System-HLS does not require one to one mapping of registers. SLEC System-HLS increases design productivity through automated setup and elimination of block-level RTL simulation.

SLEC RTL
SLEC RTL finds design errors that other tools miss by formally comparing the functionality of the original RTL design and the corresponding optimized RTL design for all possible input sequences. Unlike combinational equivalence checkers, SLEC RTL does not require one to one mapping of registers. SLEC RTL is ideal for verifying RTL changes for retiming and clock gating, allowing designers to confidently make complex changes to their RTL to meet today’s aggressive power and performance design goals.

SLEC CG
SLEC CG provides efficient, comprehensive verification of PowerPro CG optimized RTL. SLEC CG formally compares the functionality of the original RTL design with the PowerPro CG optimized RTL design for all possible input sequences. Unlike combinational equivalence checkers, SLEC CG does not require one to one mapping of registers.

PowerPro Tips & Tricks

So you've run PowerPro CG on your RTL and PowerPro CG found a number of sequential clock gating enable conditions to optimize power. You may want to take a look at just what kind of optimizations PowerPro CG has come up with.

PowerPro CG results can be easily analyzed with PowerPro Analyzer. Here's a way to investigate an observability optimization.

  1. Start the analyzer after running insert_observabilty_logic. The default view shows the newly created enables in a table, along with their CG domain number.
  2. Click on the CG domain number to pop up a summary of the CG domain. This will show the enable expression for the optimization. In some cases, this may be all the information you need to understand the optimization.
  3. In other cases, such as when the enable expression is very complex or you aren't familiar with the RTL, the best way to understand the optimization is to use the schematic viewer. Click on the enable to investigate and the schematic will jump to the driving pin of the enable in a module inserted by PowerPro CG.
  4. The schematic can be somewhat complex. To focus on the area of interest, right click on the CG module and select “New Schematic->Current Item”.
  5. Next, right click on the CG module and choose “Show Hier Contents”. This expands the logic inside the module and shows the schematic of the enable expression.
  6. Right click on the enable pin and choose “Fanout->Stop at Flops”.
  7. To see all the pins of a flop, hold ctrl+shift and double click the flop.
  8. Continue to trace the fanout from the flops (possibly through additional flops) and look for an observability point where the signal is not used by downstream logic under a certain condition. This is often a mux or a flop with a write enable.
  9. From these observability points, trace the control which creates the not-observable condition back (including through flops) and look for a place where the signal you are tracing back feeds into the CG module and the enable expression you are analyzing.

At this point you will have a schematic representation of all the logic related to the optimization. This method will make it easy to understand PowerPro CG optimizations.

Contributed by Ben Byron, Field Applications Engineer

Message from the Chief Executive Officer (continued)

On May 1, we launched our redesigned website www.calypto.com. With a new look, improved navigation, updated product information, and new features, customers will be able to access a wealth of information with a simple click of the mouse. We look forward to seeing you at DAC 2008 in Anaheim. Our booth (#1354) will feature new and exciting demonstrations of both PowerPro CG and SLEC. We will also showcase our products in action at several market makers. In addition, we will be giving away a utility called PowerPro-filer that analyzes how well a block has been optimized for power. Please see our web site (http://www.calypto.com/events.php) for more information on Calypto at DAC and to sign up for a private demonstration.

We value your interest and feedback. You can contact us at: .

Best Regards,
Tom Sandoval
Chief Executive Officer
Calypto Design Systems

May 2008 Issue

45th Design Automation Conference
in Anaheim, Ca.

Come see how Calypto's advanced RTL power optimization and functional verification products enable our customers to dramatically reduce power and improve design quality. Our technical experts will be presenting customer successes and answering questions about our PowerPro CG and SLEC products.

Come see us June 9 - 13, 2008 in Booth #1354

Register for a product demonstration at: www.calypto.com/events.php

SLEC Tips & Tricks

USING SLEC SYSTEM-HLS IN A FORTE FLOW
Central to SLEC System-HLS is Cyn2slec which allows Forte Cynthesizer users to automatically generate a SLEC Tcl file. The Cyn2slec utility extracts information about both the input SystemC design and the generated RTL via the Cynthesizer API, allowing designers to easily and quickly run SLEC to verify that the RTL implementation created by Forte Cynthesizer is equivalent to the source SystemC design. This article gives a brief overview of the cyn2slec flow, and provide specific guidance on a feature of the flow that allows additional user input to augment the information from the API to give faster proofs.

Read more >>

Calypto in the News

5.6.2008 - More good news - Calypto reports record bookings

03.24.08 - SOCcentral - Calypto Releases PowerPro CG 2.0

02.11.08 - EETimes - Hardware Design Using ESL

01.06.08 - Portable Design- Designing Energy-Efficient Consumer Electronics

12.14.07 - EDN - EDN Hot 100 Products of 2007

SLEC Tips & Tricks (continued)

A common Cynthesizer / SLEC flow looks like the following:

  1. Run Forte Cynthesizer
  2. Run cyn2slec
  3. Run SLEC

The cyn2slec command needs the design name, configuration, and reset port as inputs. The SLEC documentation fully describes additional cyn2slec command options for controlling such things as proof mode, output filename, applying constants, and overriding throughput and latency values.

A feature of the SLEC Tcl file generated by cyn2slec allows the user to specify additional SLEC commands, options, and/or flop maps, above and beyond those provided by Cyn2slec. The SLEC Tcl file contains the following lines:

#
# Source any user-supplied constraints file
set constraint_file ./slec_constraints.tcl
if {[file exists $constraint_file]} {
   echo "**************************"
   echo "Reading user-supplied constraint file $constraint_file"
   source $constraint_file
   echo "**************************"
}

If the file "slec_constraint.tcl" exists in the current directory, it will be included before the verify command is executed.

Changing Default SLEC Options
A common use of the slec_constraints.tcl file is to change the default reset checking. It is often the case that users optimize area in an RTL implementation by using flops which do not have a reset. However, the default behavior of SystemC is to reset types such as sc_int to zero. This can result in a 0 to X flop mismatch when SLEC analyzes the designs.

Adding the following option to slec_constraints.tcl would tell SLEC to allow this mismatch.
  set_global flop_checking_at_reset relaxed
This setting should then be applied each and every time SLEC is run.

Adding additional flop maps
If the design contains internal RAMs or ROMs, they are represented as an array (of flops) in the SystemC design, but as a memory block in the RTL design. Since the memory block is not a flip-flop, Cyn2slec will not create a flop map between it and the flops in the system C design. The lack of flop maps could lead to longer runtimes. The config_find_flop_map feature of SLEC will find these flop maps. These maps can then be added to slec_constraints.tcl to improve the run time. The following methodology would be used:

  • add config_find_flop_maps to slec.tcl
  • execute "slec slec.tcl" to generate slec_generated_flop_maps.tcl
  • copy the contents of slec_generated_flop_maps.tcl to slec_constraints.tcl
  • remove the config_find_flop_maps from slec.tcl and re-run

The flop maps found by SLEC would be applied in addition to those already in the slec.tcl script, resulting in improved run times.

Contributed by Duncan MacKay
Sr. Member of Consulting Staff







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