Message from the Chief Executive Officer
Happy New Year to you and your families! I hope you had a very prosperous 2007 and that your 2008 is even more successful. This past year has been filled with exciting news from Calypto and we expect 2008 will be much the same. SLEC™ usage continues to accelerate among the leaders in the electronics industry. Meanwhile, PowerPro™ CG's early adoption rate has surpassed our expectations.

In December, PowerPro™ CG was named to EDN Magazine's Top 100 Products of the Year. This is an annual listing by EDN's editors of the year's most significant products. We are very proud of this achievement which once again highlights the uniqueness of Calypto's Sequential Analysis technology.

This holiday season has once again shown that consumers have an insatiable demand for portable electronics. Power, of course, is the number one design concern for these devices and PowerPro continues to show outstanding results in reducing power for SOC's used in portable electronic applications. PowerPro is now part of mainstream design flows at several customers.

To kick off 2008, we have introduced our new SLEC System-HLS product which provides comprehensive verification of High Level Synthesis (HLS) output. More information on this new SLEC product is provided by Mitch Dale's article in this issue of the Continuum Newsletter.

Read more…

SLEC 3.0 NOW AVAILABLE

SLEC 3.0 was released on January 16th and is available for download on the Calypto FTP site. If you do not have a login or password please contact your local account manager.

SLEC 3.0 contains the new SLEC System-HLS product which tightly integrates SLEC with Mentor Catapult C and Forte Cynthesizer flows. This new product increases capacity and improves interface setup and flop mapping.

There are many additional features and enhancements for RTL and System use modes in the latest release. Read, "What's New in SLEC" or check out the release notes contained in the software release package.

Tips & Tricks

Configuring custom waveform trace setups in SLEC
Contributed by Dave Moser, Senior Field Applications Engineer

A picture is worth a thousand words. When debugging a counter-example, having the right signals arranged intuitively in the waveform viewer gives a clear picture of a falsification. While setting up a waveform viewer such as Verdi from Novas is not hard, it can be time consuming and tedious when repeated several times a day. Thankfully, there is a way in SLEC to configure the waveform viewer once and save the trace signal setup for future displays.

The command for viewing waveforms from inside SLEC is view_waveform. It should be noted that the waveform files must first be generated in SLEC by either using the config_trace_files command with -simdump option (not enabled by default) or by executing the testbench using the run_testbench command. More details on these commands can be found in the SLEC command reference manual. At this point you can arrange the trace signals in the Verdi window and debug the falsification. To save your setup follow these instructions.
  1. From within the Verdi tool save the spec and/or impl waveforms using "File/Save Signals" from within the nWave waveform viewer.

  2. Create a new directory somewhere other than the Calypto directory (which will be over-written the next time SLEC is run) and copy the waveform signal files to the new directory.

    Example:

       mkdir ../wave_files
       cp -r *wave*rc ../wave_files

  3. Add global novas_signal_files_directory to the SLEC script file and point to the new directory where the waveform signal files were copied. The pathname used here is relative to the ./Calypto directory.

    Example:

       set_global novas_signal_files_directory ../wave_file

You have now saved the trace signal setup and told SLEC to use that configuration next time the waveform viewer is opened. Any subsequent saves from within nWave will default to the new signal traces file, so there is no need to repeat the above when adding or removing signals.

Happy viewing,
Dave Moser, Senior Field Applications Engineer
Calypto in the News

01.14.08 - Yahoo Finance - Calypto Adds SLEC System-HLS to Product Line, Enabling ESL, Capturing Growing Market
SLEC System-HLS tightly integrates SLEC System into HLS design flows by automating setup and supporting HLS language extensions, such as Algorithmic C™ datatypes from Mentor Graphics® and System C Modular Interfaces from Forte Design Systems.

01.14.08 - Yahoo Finance - Mentor Graphics and Calypto Design Systems Announce Customer-Proven Electronic System Level Synthesis and Verification Flow Featuring Catapult C Synthesis and SLEC Sequential Equivalence Checker
Mentor Graphics Corporation today announced the availability of a new electronic system level (ESL) hardware design and verification flow featuring Mentor's Catapult® C Synthesis tool and Calypto Design Systems' SLEC sequential equivalence checker.

01.06.08 - Portable Design - Designing Energy-Efficient Consumer Electronics
"The migration of electronics from technology centers to consumer markets has undeniably changed the world we live in. But, putting "consumer" into consumer electronics is not just about picking the right application," states Devadas Varma, CSO, Calypto Design Systems.

12.14.07 - EDN - EDN Hot 100 Products of 2007
PowerPro CG tops the list!

12.03.07 - EETimes - Leveraging system models for RTL functional verification
"Register Transfer Level (RTL) verification remains the bottleneck in digital hardware design. Industry surveys show that functional verification accounts for 70 percent of the total design effort," said Jerome Bortolami, Sr.FAE, Calypto Design Systems.

11.5.07 - Electronic Design - Stanch The Bleeding Of Leakage Power At 65 nm
"The growing emphasis on multicore architectures is an important trend to watch. Anmol Mathur, chief technology officer at Calypto Design, points out that leakage is significantly reduced by moving to multicore architectures," states David Maliniak.

10.19.07 - EETimes - Viewpoint: RTL-ers should move to ESL
"Fifteen years ago, designers were buzzing about a new design approach: Register Transfer Level (RTL) Design. There was a fundamental change underway in how chip designs were created and implemented," states Tom Sandoval, CEO, Calypto Design Systems.
Message from the Chief Executive Officer (continued)

As more companies adopt HLS for RTL creation into their design flows, SLEC's importance to ensuring designs are bug-free has only increased. The common model of using SLEC to verify that the resulting RTL is functionally identical to the associated C model continues to be critical to the flow. In addition, a new application of SLEC has emerged. Designers are required to make changes to their original algorithmic C model to create the input required by HLS for efficient synthesis. SLEC is now being used to ensure functional equivalence between the original algorithmic C model and the C model that is fed into the HLS tool. Many functional discrepancies have already been found in customer C models using SLEC in this new application.

In 2008, Calypto will continue to provide our customers with the outstanding support we are known for. We will also continue to expand our field organization to ensure customers are using the latest techniques available to enhance their ESL methods and to design the lowest power devices possible. PowerPro will extend its industry leading power optimization capability by expanding the use of sequential analysis to uncover additional opportunities to reduce dynamic power. SLEC will extend its lead in sequential equivalence checking by expanding its design capacity and improving the efficiency of its execution. Stay tuned!

We value your interest and feedback. You can contact us at .

Best wishes for the New Year!

Tom Sandoval
Chief Executive Officer
Calypto Design Systems
What's New in SLEC for 2008

The New Year is here and so is the latest SLEC product. SLEC System-HLS, which was released last week, provides designers with comprehensive verification of High-Level Synthesis (HLS) output. Enabling ESL™, SLEC System-HLS is part of the 3.0 software release.

With Electronic System Level (ESL) tools being used on customer's flagship SOC designs there is a requirement to ensure 100% functional equivalence between the RTL output from HLS and the original system-level code. SLEC System-HLS is the result of Calypto's committed investment, cooperative partnerships and customer experience in creating a complete HLS flow.

SLEC System-HLS adds functionality to SLEC System in the areas of language support and capacity for HLS designs. Features to support Algorithmic C™ datatypes from Mentor Graphics® and System C Modular Interfaces from Forte Design Systems align SLEC with customer's HLS coding styles. By optimizing SLEC's formal engines for HLS design styles we have increased capacity to over one million gates.

Read more…
Verification based on System Models

SLEC System is the only equivalence checker on the market that can verify a RTL hardware design against a system model written in C/C++. Most design teams create and extensively verify their system models at the beginning of a design process. These system models are sometimes called the executable specification or golden model.

These golden models are perfect for equivalence checking. The only questions is, "Do these system models fit the supported language subset?"

Thanks to new system language processing enhancements, SLEC now supports a broader set of system models including those with pointers, virtual functions, C++ inheritance and polymorphism.

With release 3.0, SLEC System imposes no additional restrictions on pointer usage beyond those imposed by the C/C++ language itself. For dynamic memory allocation, an upper bound on the possible size of the memory is automatically inferred by the tool or the user can provide a tighter bound for the size of the memory. C++ language features associated with polymorphism such as public and private inheritance, virtual functions, dynamic typecasts are all handled by SLEC System.

Read more…
Product Information

SLEC System
Enabling ESL™
SLEC System enables Electronic System Level (ESL) flows by functionally verifying RTL hardware implementations using system-level models written in SystemC / C++. SLEC System comprehensively verifies RTL implementations without the need for writing testbenches or running simulation.

SLEC System-HLS
SLEC System-HLS tightly integrates SLEC System into High Level Synthesis (HLS) design flows by automating SLEC setup and supporting HLS language extensions, such as Algorithmic C™ datatypes from Mentor Graphics® and System C Modular Interfaces from Forte™ Design Systems.

SLEC RTL
SLEC RTL ensures that sequential RTL optimizations for power and timing do not introduce design bugs. SLEC RTL reduces debug time and increase designer confidence when making clock gating and retiming changes.

SLEC CG
SLEC CG comprehensively verifies PowerPro output. SLEC CG proves that under all enable and disable conditions, the PowerPro optimized RTL functions exactly the same as the original RTL.

PowerPro CG
PowerPro CG is an automated RTL power optimization solution that dramatically reduces power with little or no impact on timing or area. PowerPro CG reduces power by applying Calypto's patented Sequential Analysis Technology to identify micro-architectural changes that result in a lower power circuit.

What's new in SLEC for 2008 (continued)

The SLEC 3.0 release also includes many other system level and VHDL enhancements. Specifically, system language extensions such as pointers, dynamic memory allocation and virtual functions push SLEC's capability beyond the established synthesizable language subset. In VHDL we have added extensions for supporting multi-dimensional arrays, records and subtypes. Overall, look for significant improvements in VHDL and system level language processing robustness and build times.

On the debug front, you will notice a change in the SLEC use model. This enhancement allows users to identify and resolve problems within the SLEC TCL shell. Now when SLEC encounters an error it will not automatically exit. Instead it will stop, allowing users to examine the issue live rather than having to rerun or dig through output files. Likewise, on a design falsification, the shell will not exit automatically so the user can issue multiple waveform and testbench commands within the current session.

New to SLEC RTL is additional design consistency checking of clock gating enable logic. We have expanded SLEC's ability to identify logic that can potentially cause glitches in the clock path. SLEC will now report these conditions along with the design instance so users can easily track down issues prior to starting RTL synthesis.

With new products, new features, enhancements and overall improvements, SLEC release 3.0 has a lot to offer. I recommend upgrading as soon as possible to realize the benefits of this new software release.

Contributed by,
Mitch Dale, Director of Product Marketing



Verification based on System Models (continued)

Below is a small example of a system level model in C++ and its hardware implementation in Verilog that demonstrate the dynamic range of abstraction and sequential differences SLEC can handle. The system model has parameters which can be varied to explore various designs. The system model has pointers for fast simulation and polymorphism to make the code modular. The hardware implementation on the other hand has completely different constraints to optimize speed and power consumption of the hardware. Although the two models represent the same functionality, they are written uniquely in their native language. SLEC System can prove that the two models are equivalent for all possible inputs without simulating the two models. Because of the number of possible inputs it would not be feasible to exhaustively test equivalence with simulation.

System Model in C/C++
--------------------------------

  class FirInterface
  {
      public:
         virtual void DoFir( int data ) = 0;
   };

  class FirImple: public FirInterface
  {
      public :
         FirImplementation( int Ntaps );
         virtual void DoFir( int data );
      private :
         int * taps_;
         int * coefficients_;
  };

  int simulate_fir(int Ntaps, int * data_stream, int Nsamples) {
      FirInterface * my_fir = new FirImplementation(Ntaps);
      for( int i = 0; i < Nsamples; ++i )
         my_fir->DoFir( data_stream[i] );
  }


Hardware Implementation in Verilog
-----------------------------------------------

  always@(posedge clock )
  begin
      for(i=0; i < 254; i = i + 1 )
         taps[i+1] <= taps[i];

      for (i =0; i < 256 ; i = i + 1 )
         sum = sum + taps[i] * coefficients[i];

      out <= sum;


Contributed by,
Malay Haldar, Senior Engineering Manager



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