Message from the Chief Executive Officer
Welcome to the fall edition of the Continuum Newsletter. As 2007 races along, Calypto's power optimization and functional verification products continue to provide unique value to our growing customer base.

Design for power continues to be top of mind for SoC designers. Whether designing a modem function for a mobile phone or a traffic manager for a high end communications switch, the integration capabilities at 0.65 micron are driving an unprecedented demand for power optimization solutions. Although gate level/combinational power reduction methods may have been satisfactory for SoC design in the past, today's power reduction needs require the use of Sequential Analysis to uncover all possible opportunities to reduce power.

The capabilities of PowerPro CG continue to expand. Calypto released PowerPro CG 1.1 this past week, further extending our lead in RTL power optimization. PowerPro CG is delivering 10% to 60% power reduction across applications and improving SoC designer productivity without impacting timing or area.

Read more…

SLEC 2.3 NOW AVAILABLE

SLEC 2.3 is the latest SLEC offering from Calypto. SLEC 2.3 was released on Sept. 1st. This release improves usability and capacity. It also contains the beta release of our new elaboration based system language front-end. To participate in the new system language front-end beta program, please contact your local account manager. Some of the new features in SLEC 2.3 include:

  • Ability to automatically open the Novas Verdi tool preloaded with the signals and source code
  • Makefile driven testebenches for reproducing counter examples in simulation
  • Improvements to formal solvers which increase capacity and reduce runtime by up to 60% in HLS design styles.
  • Automated cut refinement flow for SLEC RTL
The release notes contained in the software release have a complete list of enhancements and features.

Tips & Tricks

Using "cut at mapped flops" to verify large blocks in SLEC RTL.
Contributed by Uday Das

The verify command in a SLEC TCL script starts the formal equivalence checking process. The verify command has two modes of operation: bug finding and full proof. Bug finding, also called bounded proof mode or Bounded Equivalence Checking (BEC), is useful to quickly find bugs in the design. Full proof mode is used in high level synthesis flows to provide comprehensive verification. Designers should always run bug finding mode first, fix any design bugs found and then switch to full proof mode.

Because of design size and the inherent limits of formal algorithms, full proof mode can hit capacity or runtime limits. Fortunately, if this happens, there are several different methods to reduce problem complexity and achieve a full proof. The simplest and most useful method is mapping as many flops between the two designs as possible. An additional method is to cut at mapped flops. With both methods, when a full proof is achieved, the designs are proven equivalent for all inputs over all time.

An issue to be aware of is that cut at mapped flops can generate a false negative counter example. False negatives occur because the relationship between flops at the cut point is lost. For example, if the flops at the cut point are part of a one-hot state variable after the cut, SLEC can drive all the state variable bits high, creating an illegal design state. This illegal design state may generate a false negative counter example for the user to debug.

To eliminate the debugging and resolution of false negatives, SLEC has a capability called cut refinement.

Cut refinement works with a cut at mapped flop methodology. Cut refinement is a feature in SLEC. When cut refinement is enabled and SLEC finds a counter example, the flop map pairs that caused the false negative are identified. With this information, SLEC automatically generates a TCL file with the suspect cut at mapped flop commands removed. SLEC is then rerun using the generated file slec_refined_flop_maps.tcl. This process can be repeated in a loop until user gets a full proof or a valid falsification.
Calypto in the News

Oct. 19 - EETimes - Viewpoint: RTL-ers should move to ESL
"Fifteen years ago, designers were buzzing about a new design approach: Register Transfer Level (RTL) Design. There was a fundamental change underway in how chip designs were created and implemented," states Tom Sandoval, CEO, Calypto Design Systems.

Apr. 10 - EETimes - Calypto power optimizer supports CPF
"The current EDA industry division over low power standards hasn't stopped Calypto Design Systems from announcing support for the Common Power Format (CPF) developed by Cadence Design Systems," states Richard Goering.

Mar. 23 - Calypto Debuts Sequential Power Optimization Solution for Automated RTL Power Reduction
"PowerPro CG has shown substantial power savings on designs, including blocks already manually optimized for low power by RTL designers," said Dan Smith, Director, Hardware Engineering, NVIDIA Corporation.

Mar. 14 - SOC Central - Calypto's SLEC™ product selected by AMD to verify advanced processors
"Our microprocessor design teams are consistently innovating to increase overall performance and deliver industry-leading performance-per-watt," says Nihar Mohapatra, design verification lead, AMD. "The fast, comprehensive verification which Calypto's SLEC™ provides enhances this creative process, helping our design teams continue to meet the processing needs of our customers."
Message from the Chief Executive Officer (continued)

The use of SLEC to functionally verify RTL continues to grow rapidly. We added two new SLEC customers in our most recent quarter, while dramatically expanding the use of both SLEC RTL and SLEC System in our existing customer base. Although much of SLEC System's current usage is associated with customers who have manually written their RTL code, there are definite signs that High Level Synthesis (HLS) usage is gaining momentum.

Our partnerships with Forte and Mentor continue to expand. SLEC is the only formal verification solution for HLS, and Calypto is working closely with both Mentor and Forte to ensure SLEC provides comprehensive verification for HLS output as customers continue to push the limits of HLS technology.

In the past 18 months, nearly 100 SoCs have been taken to silicon using HLS tools. In North America, several large electronics companies are now using HLS as part of their mainstream design flow on multiple projects. SoC designers recognize and experience the productivity benefits of designing at the System Level, using HLS to create the RTL code and SLEC to verify that the RTL functionality is correct.

I hope you find this latest issue of the Continuum Newsletter to be useful in understanding how Calypto's products, based on our patented Sequential Analysis Technology, can benefit your ESL verification and power optimization flows. The newsletter contains the most recent articles and news from Calypto and our partners. Please contact us at with any questions or comments.


Tom Sandoval
Chief Executive Officer
Calypto Design Systems
PowerPro CG 1.1 NOW AVAILABLE

PowerPro CG 1.1 was shipped to customers on Oct 12th. This release contains several new customer driven features and enhancements to the original 1.0 capabilities such as improvements in QOR and reporting. We have also added a tutorial that walks through the PowerPro flow. Here is a partial list of new features:
  • Enhanced write_rtl command to insert enable logic in to user RTL
  • Generation of TCL setup files to automate SLEC verification
  • Ability to specify global signals that control the enable logic of sequential clock gates
  • Reading of .powerpro file on start up and generation of history files that contain all PowerPro commands in the session
For a complete list of features and enhancements please consult the release notes and user manual included in the software release package.
Do you know the clock gating efficiency of your design?

A challenge for dynamic power reduction is knowing where and when to insert clock gates. The traditional method of looking at the percentage of registers clock gated is not indicative of power reduction because it does not take into account switching activity. The average clock gating efficiency is a much better indicator of dynamic power consumption because it measures both the number of registers and the duration of how long those registers are gated.

Click here to learn more about clock gating efficiency.

Understanding Sequential Analysis

SLEC and PowerPro product lines are based on Calypto's unique, patented sequential analysis technology.

Sequential analysis is the process of observing functional behavior over time. Applied to RTL, sequential analysis computes the temporal relationships between design states across multiple clock cycles. Our design and verification tools take advantage of these relationships.

Read more…
Product Information

SLEC System
SLEC SYSTEM proves functional equivalence or locates differences between system-level models written in SystemC / C++ and RTL design descriptions. SLEC SYSTEM enables system-level design flows, transferring the confidence of previous system-level simulations to subsequent RTL implementations.

SLEC RTL
SLEC RTL verifies functionality by comparing an RTL design specification against a 'golden' reference design. If the designs are not functionally equivalent, SLEC RTL detects the design difference and immediately generates a counter-example for debug. SLEC RTL ensures functional correctness of micro-architectural optimizations, giving designers confidence and immediate feedback when making RTL changes.

PowerPro CG
PowerPro CG is an automated RTL power optimization solution that dramatically reduces power with little or no impact on timing or area. PowerPro CG reduces power by applying Calypto's patented Sequential Analysis Technology to identify micro-architectural changes that result in a lower power circuit.

Sequential Analysis (continued)

Calypto's SLEC product combines sequential analysis with formal proof technology to enable sequential equivalence between designs that have completely different state and timing representation. For example, SLEC System can verify a cycle accurate timed RTL implementation against models written in C/C++ or System C. Similarly, SLEC RTL can verify RTL designs with retiming or clock gating changes.

Calypto's PowerPro product uses sequential analysis to identify enable conditions that span multiple cycles. These conditions can become very complex, making them difficult to identify when compared to combinational clock gating.

PowerPro CG reduces switching activity by taking advantage of existing inefficiencies in the RTL code such as unused computation, data dependent functions and don't-care cycles. There are many forms of sequential clock gating transformations that reduced switching activity. These include conditions such as data being written to registers in the current clock cycle that will not be used in later clock cycles.

Until recently, sequential clock gating required manual identification and implementation. Now, with PowerPro CG, designers have access to advanced automated, low-power design techniques, eliminating the often difficult and error-prone manual methods.

Sequential analysis technology has many applications in EDA. It provides greater insight into design functionality; allowing tools to further decompose and utilizes aspects in the design not seen by previous technologies. Calypto first commercialized sequential analysis in 2004 and we continue work with to Universities worldwide to advance the technology.



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