Message from the Chief Executive Officer
Welcome to the summer edition of the Continuum Newsletter.  We have much to report so let's get right to it.

DAC 2007 in early June confirmed that the key design consideration for today's SoC designers is in fact power.  We have seen an overwhelming interest in our new PowerPro CG product which has reduced power by as much as 60% in customer design blocks.  PowerPro CG uses Calypto's patented Sequential Analysis Technology to identify clock gating opportunities within an RTL block and produce a new RTL model optimized for power with little or no impact to timing, area or leakage power.  The technology is being embraced by market leaders in the areas of networking, wireless, multimedia, and graphics.

In addition to the interest in PowerPro CG, the unique capabilities of SLEC continue to draw industry praise.  Designers have embraced SLEC as the defacto standard for RTL verification in system level design flows.  Our annual survey at DAC indicated that 77% of designers use system-level models for SoC design, nearly a 10% increase over last year's survey results.  The survey also validated the market need for SLEC, revealing that 71% of those designers use their system models to verify the corresponding RTL implementation.  In addition, over 60% of DAC attendees surveyed work in North America, further evidence that ESL continues its dramatic growth in the geography.

Read more…
Introducing PowerPro CG

PowerPro CG is an automated RTL power optimization solution that dramatically reduces power with little or no impact on timing or area.  PowerPro CG reduces power by applying Calypto's patented Sequential Analysis Technology to identify micro-architectural changes that result in a lower power circuit.

Benefits
  • Automates sequential clock gating to reduce dynamic power
  • Operates at the RTL for maximum power savings
  • Fits into existing RTL design flows
Read the EETimes review of PowerPro CG - Mar. 07 Power tool taps clock gating.
Calypto in the News

Mar. 23 - Calypto Debuts Sequential Power Optimization Solution for Automated RTL Power Reduction
"PowerPro CG has shown substantial power savings on designs, including blocks already manually optimized for low power by RTL designers," said Dan Smith, Director, Hardware Engineering, NVIDIA Corporation.

Mar. 14 SOC Central - Calypto's SLEC product selected by AMD to verify advanced processors
"Our microprocessor design teams are consistently innovating to increase overall performance and deliver industry-leading performance-per-watt," says Nihar Mohapatra, design verification lead, AMD. "The fast, comprehensive verification which Calypto's SLEC provides enhances this creative process, helping our design teams continue to meet the processing needs of our customers."

Partner News

Apr. 10 EETimes - Calypto power optimizer supports CPF
"The current EDA industry division over low power standards hasn't stopped Calypto Design Systems from announcing support for the Common Power Format (CPF) developed by Cadence Design Systems," states Richard Goering.

Forte Cynthesizer Integration
Forte's 'cynw_p2p' interface is a point to point transaction based interface protocol.  This allows designers to capture algorithms in SystemC without worrying about to the details of inter block communication.

SLEC supports design written with cynw_p2p interfaces. In these designs SLEC ensures the synthesized RTL accurately represents the algorithm and the communication protocol defined in the SystemC reference model.

Additional details on SLEC's support for Forte Cynthesizer design can be found in the SLEC application notes.
Message from the Chief Executive Officer (continued)

On the business front, we closed our 4th quarter with record sales for both the quarter and our 2007 fiscal year.  Both revenues and new licenses for SLEC more than doubled over 2006.  Based on the increasing demand for SLEC to verify RTL blocks and the tremendous industry wide excitement over our new PowerPro CG product, we are confident that FY2008 will be exceptional year for Calypto.

With that in mind, we continue to expand our sales, marketing, and applications teams, and have recently hired Doug Aitelli to run worldwide sales for Calypto.  Doug's outstanding track record in sales management and strategic account development makes him the ideal person to lead Calypto's sales efforts.  His professional sales experience will be a key asset as we expand Calypto's market presence.

I hope you find this latest issue of the Continuum Newsletter to be helpful in understanding Calypto's products and capabilities.  The newsletter contains the most recent articles and news from Calypto and our partners.  Please contact us at info@calypto.com. with any questions or comments.

Enjoy the summer!

Tom Sandoval
Chief Executive Officer
Calypto Design Systems
SLEC 2.2 NOW AVAILABLE

SLEC 2.2 extends the capability, improves designer productivity and increases runtime performance for all SLEC products.  These new features include:
  • VHDL testbench enhancements for ModelSim and NC-VHDL simulation environments. New makefile targets automate the testbench debugging process reducing the effort to debug counter-examples generated when SLEC finds design differences.
  • Forte Modular Interface Support for TLM interfaces. Designs written with the Forte cynw_p2p modular interface classes can be verified using SLEC 2.2.
  • Enhanced reporting features provide additional detail for faster diagnosis and debugging of design differences.
The SLEC 2.2 release notes contain a complete list of enhancements and features.
Tips & Tricks For SLEC

We have added a new feature in the Continuum Newsletter from our product experts. Tips & Tricks will become a regular section that provides best practices and innovative solutions for using SLEC and PowerPro. This issue's tip on managing source files was contributed by Shusaku Yamamoto.

One of the first commands in a SLEC script is 'build_design'. It is the entrance to SLEC world. This command parses the design files into the SLEC intermediate database.

A typical example of the usages of the build_design command is: 
  build_design -spec -systemc -DWIDTH=20 \
   -I.\
   -I/home/our_project/common/include
   -I/home/our_project/video_common/include \
   /home/foo/my_block.cpp \
   /home/foo/his_block_1.cpp \
   /home/foo/his_block_2.cpp

  build_design -impl -verilog +define+WIDTH=20 \
   -y /home/semi_A/Lib_cell/rtl \
   -y /home/semi_A/Lib_mem/rtl \
   /home/foo/rtl/his_block_1.v\
   /home/foo/rtl/his_block_2.v
   my_block.v
Read more…
Additional Product Information

SLEC System
SLEC SYSTEM proves functional equivalence or locates differences between system-level models written in SystemC / C++ and RTL design descriptions. SLEC SYSTEM enables system-level design flows, transferring the confidence of previous system-level simulations to subsequent RTL implementations.

SLEC RTL
SLEC RTL verifies functionality by comparing an RTL design specification against a 'golden' reference design. If the designs are not functionally equivalent, SLEC RTL detects the design difference and immediately generates a counter-example for debug. SLEC RTL ensures functional correctness of micro-architectural optimizations, giving designers confidence and immediate feedback when making RTL changes

SLEC CG
SLEC CG is a sequential equivalence checker that functionally verifies block-level clock gating changes in Verilog and VHDL designs. SLEC CG verifies RTL clock gating changes by comparing an original RTL model to a corresponding clock gated RTL model using sequential analysis technology.

Tips and Tricks (continued)

The 'build_design' arguments depend on the file-system directory structure. Typing full paths in file names is error prone and makes it cumbersome to relocated files later. A cleaner approach is to use "pushd and popd", "$testdir" and "$env()"
  • pushd and popd behaviors in TCL are the same as Unix. You can change directories while pushing the previous directory on a stack with pushd and then return to that directory by poping it from the stack with popd.
  • $testdir is SLEC defined system variable which points SLEC executed directory
  • $env() is TCL system variable which gets the Unix shell system variable's.
By incorporating these utilities with the build_design the previous code can be modified as follows:

  pushd /home/foo
    build_design -spec -systemc -DWIDTH=20 \
      -I$testdir \
      -I$env(OUR_PROJECT)/common/include \
      -I$env(OUR_PROJECT)/video_common/include \
      my_block.cpp \
      his_block_1.cpp \
      his_block_2.cpp
  popd

  pushd /home/foo/rtl
    build_design -impl -verilog +define+WIDTH=20 \
      -y $env(SEMI_A_LIB_HOME)/Lib_cell/rtl \
      -y $env(SEMI_A_LIB_HOME)/Lib_mem/rtl \
      his_block_1.v\
      his_block_2.v
      $testdir/rtl/my_block.v
  popd

 By using this method the new "build_design" code has enhanced portability and is much easier to read.

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