Calypto in the News

03/24/08 SOC Central - Calypto Releases PowerPro CG 2.0 

02/11/08 EETimes - Hardware design using ESL

01/06/08 Portable Design - Designing Energy-Efficient Consumer Electronics

12/14/07 EDN - EDN Hot 100 Products of 2007

12/03/07 EETimes - Leveraging System Models for RTL Functional Verification

11/05/07 Electronic Design - Stanch The Bleeding Of Leakage Power At 65 nm

10/19/07 EETimes - Viewpoint: RTL-ers should move to ESL

10/05/07 Design and Reuse - How effective use of ESL tools can increase your HW/SW system design productivity

04/10/07 EETimes - Calypto power optimizer supports CPF

03/26/07 EETimes - Power tool taps clock gating

03/14/07 SOCcentral - Calypto's SLEC™ RTL Product Selected by AMD to Verify Advanced Processors

01/26/07 EE Times - Models hold value, not IP

01/20/07 Chip Design/iDESIGN - The Power of RTL Clock-gating

01/17/07 Electronic Design - Design Complexity Spurs The Need For Formal Verification

12/20/06 EE Times India - Calypto hosts seminar on ESL methods for RTL design

11/06/06 EE Times - Calypto equivalence checker eyes clock gating

10/30/06 EE Times - Larger EDA vendors are finally realizing the time for offering real ESL solutions is longoverdue

09/04/06 EDA Cafe - Tom Sandoval's Top Ten Catechisms for Venture Capital Success

08/18/06 EDACafe - Calypto - Equivalence Checking

06/22/06 Electronic Design - Sequential-Logic Equivalence Checker Gains Capacity And Speeds Up Runtimes

06/19/06 EE Times - Sequential equivalence checking for RTL models

05/22/06 EE Times - Sequential logic equivalence checker claims huge speed boost

05/15/06 EE Times - Sequential equivalence checking supports ESL flow

03/24/06 SOC Central - Re-Timing Verification Using Sequential Equivalence Checking

01/27/06 EE Times - EE Times - Calypto names former LSI Logic exec CEO

12/07/05 EE Times - Calypto sees ESL take hold in U.S.

12/05/05 EDN - SLEC chosen as one of the top 100 products of 2005.

11/14/05 EE Times - Designing hardware with C-based languages

11/01/05 EE Times - EE Times updates list of 60 emerging startups

10/25/05 EE Times - The 2005 "verification census" survey recap

10/25/05 DeepChip.com - 2005 Verification Census – Calypto SLEC

10/17/05 EE Times - ESL providers get practical

10/11/05 Nikkei Microdevices - Renesas Selects Sequential Equivalence Checker for Confidence in Functional Verification

10/07/05 Nikkei Microdevices - Sequential Equivalence Checker accelerates C based design

10/05/05 EDN Japan - New Equivalence Checker Verifies Functionality: Enables System to RTL Verification

10/04/05 SOC Central - Calypto and Forte Collaborate on Formal Verification and Behavioral Synthesis Tool Integration

10/04/05 Embedded Star - Calypto, Forte Integrate Formal Verification and Behavioral Synthesis

10/04/05
EE Times - Companies claim first integrated solution for SystemC users

10/03/05 EE Times - Verification moves to a higher level

10/01/05 DesignWave - Formal Verification tool covers SystemC

09/01/05 Electronique - Sequential Equivalence Analysis: Ready for System Level Design

09/01/05 Electronique - An Essential Brick for the Move to ESL (DAC Recap)

09/01/05 EDA Tech Forum - Verifying micro-architectural optimizations for high-performance system-on-chip designs

08/30/05 Elektronik Tidningens - New Interests for High Abstraction

08/10/05 EE Times - Startup Calypto Design Systems adds two to tech advisory board

08/01/05 Prosessori - Calypto – Novel Solution

07/01/05 Inside Chips - Calypto, Mentor Integrate Tools

06/29/05 DeepChip.com - Industry Gadfly: Post-DAC Debriefing

06/21/05 Electronic Design - Launching Into the System-To-RTL Continuum

06/13/05 Kumikomi Networks - DAC 2005 Report

06/10/05 EE Times - Must See List for DAC 2005

06/09/05 DeepChip.com - Industry Gadfly: Must See List For DAC 2005

06/06/05 SOC Central - Don't Forget the Little Guys!

06/02/05 EE Times - Startup integrates equivalence checker with Mentor's Catapult

06/02/05 SOC Central - Calypto and Mentor Graphics Integrate Tools for Verifiable, Automated Path from System to RTL

05/31/05 SOC Central - The Open SystemC Initiative and OCP-IP Join Forces to Target TLM Layer Standardization

05/12/05 Electronique International Hebdo - Verifier l'equivalence entre implantation RTL et specification systeme

05/12/05 Electronic Design - Equivalence Checker Handles Sequential Logic

05/01/05 Electronic Products News - EDA Movie: DATE 2005

05/01/05 Elettronica Oggi - Mondo Elettronico

05/01/05 Inside Chips - Calypto Launches Industry's First Sequential Equivalence Checker

04/26/05 Embedded Star - Calypto Rolls Out SLEC Sequential Logic Equivalence Checking Solution

04/25/05 Electronics Weekly - Formal Analysis at the System Level

04/25/05 EE Times - Startup preps for ESL design

04/25/05 EE Times - New verification tools intended to bridge system-level with RTL

04/25/05 EDN - EDA startup brings formal analysis to the system level

04/24/05 Hindustan Times - IIT Delhi displays R&D power to industry titans

04/21/05 Electronics News European Correspondent - Future of EDA

03/25/05 Electronic News - Design at the System Level

03/17/05 Electronic News - Design at the System Level

03/17/05 Electronique - Le nanometrique impose une evolution des methodologies de conception

03/08/05 Electronic Design - Dispatch from DATE 2005

03/01/05 Inside Chips - Emerging Ventures

02/04/05 Nikkei Microelectronics - Calypto to Reduce ASIC Development Time Through Capability to Verify Equivalence Between SystemC and RTL

02/01/05 Chip Design - People

01/27/05 EDA Nation - Citizenry

01/24/05 EE Times - Startup paves way for ESL jump

01/19/05 EE Times Asia - EDA startup preps sequential equivalency checker

01/18/05 Electronics Talk - Calypto readies its design portfolio

Newsletters

July 2008

May 2008

January 2008

October 2007

July 2007

Resources

EE Times

EDN.com

Chip Design Magazine

SOCcentral

IC Design and Verification Journal

Press Contact

Nanette Collins
Public Relations for Calypto Design Systems, Inc.
Tel: +1 617 437 1822
Email: